In certain applications, such as the management of the memory of a data processing system, a cache is utilized to maintain associated information which has different periods of utility. For example, in the paged memory management unit (PMMU) described in the several copending applications cited above, logical-to-physical address translators are maintained in a translator cache. Often, it is desired to assure rapid access to certain code/data pages. This in turn requires that the translators for these pages be available in the cache for the required period of time. One solution has been to associate with each translator in the cache a lock indicator which, when set, will preclude removal of the translator in order to make room for a different translator. When a given page is no longer needed, the PMMU can be instructed by the processor to reset the lock indicator for the translator for that page, thereby making this translator a candidate for replacement.
In some circumstances, the processing activity may be such that the cache becomes full of locked translators. In this event, the PMMU will be unable to enter any new translators into the cache. As a result, the PMMU will be effectively prevented from performing any translations for which the translator is not already in the cache. One solution to this problem is for the PMMU to interrupt the processor as soon as the last entry is locked, so that the processor can immediately take remedial action. This may be acceptable in systems wherein the memory management routines of the operating system are always accessible (e.g. because the associated translators are among those locked in the cache). An example of such a system is shown in U.S. Pat. No. 4,084,226. In general, however, this solution is inherently risky, and requires either independent means to access the memory management routines, dedication of a portion of the cache to the essential translators, or some other emergency relief mechanism.